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Abstract: As superconducting qubit performance continues to evolve, we must also address the interconnect challenge for superconducting quantum processors (SQPs). Various multi-level wiring and heterogeneous 3D integration technologies have been developed for classical integrated circuits, but they must be optimized for use with superconducting quantum systems because they contain normal metals and lossy dielectrics that can compromise the performance of superconducting qubits. We will discuss the challenges of implementing and vetting 3D heterogeneous technologies to enable extensible SQPs. Integration technologies include air-bridges for crossing signals; flip-chip integration with indium bump bonds and silicon hard-stop spacers to couple multiple chips; superconducting through silicon vias to route signals through chips and enable novel circuit elements; multilevel planarized wiring to support complex routing schemes; and multi-tier stacks which can enable complex control and readout of superconducting quantum arrays.

This material is based upon work supported by the Dept of Energy and Under Secretary of Defense for Research and Engineering under Air Force Contract No. FA8702-15-D-0001. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Dept of Energy and Under Secretary of Defense for Research and Engineering.

Hosted by Professor Chandrasekhar Ramanathan