Dartmouth Events

Abstract: Graphene is a two-dimensional carbon allotrope and promising candidate for future electronic applications. Its unconventional band structure exhibits a linear energy dispersion relation with zero band-gap, resulting in semi-relativistic charge carriers that have exceptional mobility. However, studying electron transport in graphene requires the ability to deposit the 2D layer on an insulating substrate and make reliable ohmic, low-resistance electrical contact to it. This thesis approaches that task in two main phases: first by fabricating graphene devices, and second by characterizing their electrical properties. In order to reduce the risk of damaging or contaminating the graphene sample, metal electrodes are patterned onto the SiO2 layer of a doped silicon wafer before a graphene monolayer is transferred on top. If the graphene’s inherent characteristics have been preserved within this top channel, an applied back-gate voltage can be used to tune the density of states, controlling current flow much like a field-effect transistor. Sweeping the gate should then resolve a Dirac resistivity peak where graphene's valence and conduction bands meet. This project ultimately prioritizes locating these Dirac peaks under various fabrication regimes, and lays the groundwork for future studies involving carrier dynamics in graphene.